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ds1857 dual temperature-controlled resistors with external temperature input and monitors ______________________________________________ maxim integrated products 1 for pricing delivery, and ordering information please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the ds1857 dual temperature-controlled nonvolatile (nv) variable resistors with external temperature input and monitors consists of two 50k ? 256-position linear variable resistors, two analog monitor inputs (mon1, mon2), and an external temperature sensor input. the device provides an ideal method for setting and tem- perature-compensating bias voltages and currents in control applications using minimal circuitry. the vari- able resistor settings are stored in eeprom memory and can be accessed over the 2-wire serial bus. applications optical transceivers optical transponders instrumentation and industrial controls rf power amps diagnostic monitoring features ? four total monitored channels (temperature, v cc , mon1, mon2) ? two external analog inputs (mon1, mon2) ? interface to external temperature sensor (lm50) ? two 50k ? , linear, 256-position, nonvolatile temperature-controlled variable resistors ? resistor settings changeable every 2c ? access to monitoring and id information configurable with separate device addresses ? resistor disable (open-circuit) function ? 2-wire serial interface ? three address lines for multiple devices ? operates from a 3.3v or 5v supply ? sff-8472 compatible ordering information rev 1; 6/04 part temp range pin-package ds1857e-050 -40? to +95? 16 tssop ds1857e-050/t&r -40? to +95? 16 tssop (tape-and-reel) DS1857B-050 -40? to +95? 16 ball csbga a top view b c d 1 16-ball csbga (4mm x 4mm) 1.0mm pitch 16 tssop 3 24 exttmp a0 wpen rhiz mon2 mon1 l0 gnd h1 v cc scl a1 l1 h0 sda a2 ds1857 sda 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 scl a0 a1 a2 wpen rhiz gnd v cc h1 l1 h0 l0 exttmp mon2 mon1 pin configurations ds1857 sda 1 2 3 4 5 6 7 8 16 0.1 f 15 14 13 12 11 10 9 scl a0** a1** a2** wpen rhiz gnd v cc h1 l1 h0 l0 exttmp mon2 mon1 tx disable to external temperature sensor, such as lm50 diagnostic inputs 0 to 2.5v fs to laser bias control to laser modulation control decoupling cap rx power* tx bias* *rx power and tx bias can be arbitrarily assigned to the mon inputs. **address inputs determine the main device 2-wire slave address when adfix = 0. this address must be different than the aux device address when aden = 0. v cc v cc v cc = 3.3v 4.7k ? 4.7k ? 2-wire interface ground to disable write protect t ypical operating circuit
ds1857 dual temperature-controlled resistors with external temperature input and monitors 2 _____________________________________________________________________ parameter symbol conditions min typ max units supply voltage v cc (note 1) +3.0 5.5 v input logic 1 (sda, scl, a2, a1, a0, wpen, rhiz) v ih (note 2) 0.7 x vcc v cc + 0.3 v input logic 0 (sda, scl, a2, a1, a0, wpen, rhiz) v il (note 2) -0.3 0.3 x v cc v resistor inputs (l0, l1, h0, h1) -0.3 v cc + 0.3 v resistor current i res -3 +3 ma absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc relative to ground.......................-0.5v to +6.0v voltage on inputs relative to ground* ................................................-0.5v to v cc + 0.5v voltage on resistor inputs relative to ground* ................................................-0.5v to v cc + 0.5v current into resistors............................................................5ma operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature .......................................see ipc/jedec j-std-020a specification recommended dc operating conditions (t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc (note 3) 1 2 ma input leakage i il -1 +1 ? input current each i/o pin 0.4 x v cc < v i/o < 0.9 x v cc -10 +10 ? v ol1 3ma sink current 0 0.4 low-level output voltage (sda) v ol2 6ma sink current 0 0.6 v full-scale input (mon1, mon2) (note 4) 2.4875 2.5000 2.5125 v full-scale v cc monitor (note 5) 6.5208 6.5536 6.5864 v i/o capacitance c i/o 10 pf wpen pullup resistor r wpen 40 65 100 k ? rhiz pullup resistor r rhiz 40 65 100 k ? digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.0 2.6 v dc electrical characteristics (v cc = 3.0v to 5.5v, t a = -40? to +95?, unless otherwise noted.) *not to exceed 6.0v.
ds1857 dual temperature-controlled resistors with external temperature input and monitors _____________________________________________________________________ 3 parameter symbol conditions min typ max units exttmp input voltage v exttmp 1.779 v conversion resolution ? v exttmp 625 ? conversion accuracy v exttmp (note 9) 12.8 mv external temperature (v cc = 3.0v to 5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units input resolution ? vmon 610 ? supply resolution ? v cc 1.6 mv input/supply accuracy a cc 0.25 0.5 % fs (full scale) update rate for mon1, mon2, temp, or v cc t frame 20 30 ms analog voltage monitoring (v cc = 3.0v to 5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units position 00h resistance t a = +25? 0.70 1.0 1.25 k ? position ffh resistance t a = +25? 40 50 60 k ? absolute linearity (note 6) -2 +2 lsb relative linearity (note 7) -1 +1 lsb temperature coefficient (note 8) 50 ppm/? high-z resistor current i rhiz r hiz = v cc 0.1 ? analog resistor characteristics (v cc = 3.0v to 5.5v, t a = -40? to +95?, unless otherwise noted.)
ds1857 dual temperature-controlled resistors with external temperature input and monitors 4 _____________________________________________________________________ parameter symbol conditions min typ max units fast mode (note 10) 0 400 scl clock frequency f scl standard mode (note 10) 0 100 khz fast mode (note 10) 1.3 bus free time between stop and start condition t buf standard mode (note 10) 4.7 ? fast mode (notes 10, 11) 0.6 hold time (repeated) start condition t hd:sta standard mode (notes 10, 11) 4.0 ? fast mode (note 10) 1.3 low period of scl clock t low standard mode (note 10) 4.7 ? fast mode (note 10) 0.6 high period of scl clock t high standard mode (note 10) 4.0 ? fast mode (notes 10, 12, 13) 0 0.9 data hold time t hd:dat standard mode (notes 10, 12, 13) 0 ? fast mode (note 10) 100 data setup time t su:dat standard mode (note 10) 250 ns fast mode (note 10) 0.6 start setup time t su:sta standard mode (note 10) 4.7 ? fast mode (note 13) 20 + 0.1c b 300 rise time of both sda and scl signals t f standard mode (note 13) 20 + 0.1c b 1000 ns fast mode (note 13) 20 + 0.1c b 300 fall time of both sda and scl signals t r standard mode (note 13) 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 ? capacitive load for each bus line c b (note 13) 400 pf eeprom write time t w (note 14) 10 ms ac electrical characteristics (v cc = 3.0v to 5.5v, t a = -40? to +95?, unless otherwise noted.) note 1: all voltages are referenced to ground. note 2: i/o pins of fast-mode devices must not obstruct the sda and scl lines if v cc is switched off. the address inputs should be connected to either v cc or gnd depending on the desired address setting. note 3: sda and scl are connected to v cc and all other input signals are connected to well-defined logic levels. note 4: the maximum voltage the mon inputs will read is approximately 2.5v, even if the voltage on the inputs is greater than 2.5v. note 5: this voltage is defining the maximum range of the analog-to-digital converter and not the maximum v cc voltage. note 6: absolute linearity is the difference of measured value from expected value at dac position. the expected value is a straight line from measured minimum position to measured maximum position. note 7: relative linearity is the deviation of an lsb dac setting change vs. the expected lsb change. the expected lsb change is the slope of the straight line from measured minimum position to measured maximum position. note 8: see the typical operating characteristics . note 9: the conversion accuracy does not include any error from the lm50. note 10: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000ns + 250ns = 1250ns before the scl line is released.
ds1857 dual temperature-controlled resistors with external temperature input and monitors _____________________________________________________________________ 5 ac electrical characteristics (continued) (v cc = 3.0v to 5.5v, t a = -40? to +95?, unless otherwise noted.) note 11: after this period, the first clock pulse is generated. note 12: the maximum t hd:dat only to has be met if the device does not stretch the low period (t low ) of the scl signal. note 13: a device must internally provide a hold time of at least 300ns for the sda signal (see the v ih min of the scl signal) in order to bridge the undefined region of the falling edge of scl. note 14: c b ?otal capacitance of one bus line, timing referenced to 0.9 x v cc and 0.1 x v cc . note 15: eeprom write begins after a stop condition occurs. t ypical operating characteristics (v cc = 5.0v, t a = +25?, unless otherwise noted.) supply current vs. temperature ds1857 toc01 temperature ( c) supply current ( a) 80 60 40 20 0 -20 540 580 620 660 700 500 -40 100 supply current vs. voltage ds1857 toc02 voltage (v) supply current ( a) 5.0 4.5 4.0 3.5 450 500 550 600 650 700 400 3.0 5.5 resistance vs. setting ds1857 toc03 setting resistance (k ? ) 250 200 150 100 50 10 20 30 40 50 60 0 0300 active supply current vs. scl frequency ds1857 toc04 scl frequency (khz) active supply current ( a) 300 200 100 540 580 620 660 700 500 0400 sda = 5v
ds1857 dual temperature-controlled resistors with external temperature input and monitors 6 _____________________________________________________________________ t ypical operating characteristics (continued) (v cc = 5.0v, t a = +25?, unless otherwise noted.) resistor 0 inl (lsb) ds1857 toc05 position resistor 0 inl (lsb) 225 200 150 175 50 75 100 125 25 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0250 resistor 0 dnl (lsb) ds1857 toc06 resistor 0 dnl (lsb) -0.15 -0.05 0.05 0.15 0.25 -0.25 position 225 200 150 175 50 75 100 125 25 0250 resistor 1 inl (lsb) ds1857 toc07 position resistor 1 inl (lsb) 225 200 150 175 50 75 100 125 25 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0250 resistor 1 dnl (lsb) ds1857 toc08 resistor 1 dnl (lsb) -0.15 -0.05 0.05 0.15 0.25 -0.25 position 225 200 150 175 50 75 100 125 25 0250 external temp sensor voltage vs. temperature ds1857 toc09 voltage (v) temperature ( c) 1.5 1.0 0.5 -20 0 20 40 60 80 100 120 140 -40 02.0 ppm vs. position ds1857 toc10 position ppm/ c 250 200 50 100 150 -10 40 90 140 190 240 290 340 -60 0300 +25 c to +85 c +25 c to -40 c
ds1857 dual temperature-controlled resistors with external temperature input and monitors _____________________________________________________________________ 7 detailed description the user can read the registers that monitor the v cc , mon1, mon2, and temperature analog signals. after each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. the signals also have alarm flags that notify the user when the signals go above or below the user- defined value. interrupts can also be set for each signal. the position values of each resistor can be indepen- dently programmed. the user can assign a unique value to each resistor for every 2? increment over the -40? to +102? range. both resistors can also be put in a high-impedance mode using the rhiz pin. an external temperature sense input, exttmp, con- verts an analog voltage into a digital value that repre- sents temperature. its scale is defined by +10mv/? gain and +500mv offset at 0?. this corresponds to the characteristics of the lm50 temperature sensor. the resistor look-up tables are stepped through according to this temperature every 2? from -40? to +102?. pin ball name function 1b 2 sda 2-wire serial data interface. this pin is for serial data transfer to and from the device. 2a 2 scl 2-wire serial clock interface. the serial clock input is used to clock data into and out of the device. 3c 3a 0 address input. the address input pins specify the 2-wire address of the device (when adfix = 0). 4a 1a 1 address input. the address input pins specify the 2-wire address of the device (when adfix = 0). 5b 1a 2 address input. the address input pins specify the 2-wire address of the device (when adfix = 0). 6c2 wpen write protect enable. the device is not write protected if wpen is connected to ground. this pin has an internal pullup (r wpen ) (see table 6). 7c1 rhiz resistor disable input. when high, this signal places both resistors in an off state or high impedance mode. when low, the resistors are on. this pin has an internal pullup (r rhiz ). 8d1 gnd supply ground 9d3 mon1 external analog input 10 d4 mon2 external analog input 11 c4 exttmp external temperature input. this analog signal is converted into a digital value that represents a temperature. the digitized value indexes through the look-up tables. 12 d2 l0 low-end resistor 0 terminal. it is not required that the low-end terminals be connected to a potential less than the high-end terminal of the corresponding resistor. voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, v cc , or go below ground. 13 b3 h0 high-end resistor 0 terminal. it is not required that the high-end terminals be connected to a potential greater than the low-end terminal of the corresponding resistor. voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, v cc , or go below ground. 14 b4 l1 low-end resistor 1 terminal 15 a4 h1 high-end resistor 1 terminal. 16 a3 v cc supply voltage pin descriptions
ds1857 dual temperature-controlled resistors with external temperature input and monitors 8 _____________________________________________________________________ device address ad (auxiliary device enable a0h) md (main device enable) device address address address address r/w r/w data bus r/w aden adfix sda scl 2-wire interface rhiz mon1 mon2 v cc gnd wpen eeprom 128 x 8 bit 00h-7fh standards prot aux ad address table select r/w eeprom 72 x 8 bit 80h-c7h table 02 resistor 0 look-up table prot main md eeprom 72 x 8 bit 80h-c7h sram 32 x 8 bit 60h-7fh not protected prot main md temp index alarm flags mux ctrl measurement address table select r/w eeprom 72 x 8 bit 80h-c7h table 03 resistor 1 look-up table prot main md temp index v cc r rhiz r wpen monitors limit high monitors limit low table select temp index mint (bit) exttmp v cc mux a/d 12-bit a/d ctrl v cc v cc prot aux prot main mpen apen comparator measurement alarm flags monitors limit low monitors limit high comp ctrl interrupt mint table 01 eeprom 16 x 8 bit 80h-8fh vendor prot main md r/w device address address table select masking (tmp, v cc , mon1, mon2) adfix (bit) aden (bit) mpen (bit) apen (bit) inv2 (bit) inv1 (bit) rhiz resistor 0 50k ? full scale 256 positions l0 h0 register register rhiz resistor 1 50k ? full scale 256 positions l1 h1 a0 a1 a2 figure 1. ds1857 block diagram
ds1857 dual temperature-controlled resistors with external temperature input and monitors _____________________________________________________________________ 9 monitored signals each signal (v cc , mon1, mon2, and temperature) is available as a 16-bit value with 12-bit accuracy (left-jus- tified) over the serial bus. see table 1 for signal scales and table 2 for signal format. the four lsbs should be masked when calculating the value. the signals are updated every frame rate (t frame ) in a round-robin fashion. the comparison of all four signals with the high and low user-defined values are done automatically. the corre- sponding flags are set to 1 within a specified time of the occurrence of an out-of-limit condition. calculating signal values the lsb = 100? for v cc , and the lsb = 38.147? for the mon signals. to calculate the value of v cc , convert the unsigned 16- bit value to decimal and multiply by 100?. to calculate the value of mon1 or mon2, convert the unsigned 16-bit value to decimal and multiply by 38.147?. to calculate the value of the temperature, treat the two? complement value binary number as an unsigned binary number, then convert to decimal and divide by 256. if the result is greater than or equal to 128, then subtract 256 from the result. temperature: high byte: -128 c to +127 c signed; low byte: 1/256 c. signal +fs signal +fs ( hex) -fs signal -fs ( hex) temperature 127.996 c 7fff -128 c 8000 v cc 6.55v ffff 0v 0000 mon1 2.5v ffff 0v 0000 mon2 2.5v ffff 0v 0000 table 1. scales for monitor channels signal format v cc unsigned mon1 unsigned mon2 unsigned temperature two? complement table 2. signal comparison temperature corresponding look-up table address <-40 c 80h -40 c 80h -38 c 81h -36 c 82h -34 c 83h +98 c c5h +100 c c6h +102 c c7h >+102 c c7h table 3. look-up table address for corresponding temperature values msb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 lsb 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb (bin) lsb (bin) voltage (v) 10000000 10000000 3.29 11000000 11111000 4.94 s2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 msb (bin) lsb (bin) temperature ( c) 01000000 00000000 64 01000000 00001111 64.059 01011111 00000000 95 11110110 00000000 -10 11011000 00000000 -40 msb (bin) lsb (bin) voltage (v) 11000000 00000000 1.875 10000000 10000000 1.255 monitor v cc bit weights temperature bit weights temperature conversion example v cc conversion example monitor conversion example
ds1857 dual temperature-controlled resistors with external temperature input and monitors 10 ____________________________________________________________________ aden (address enable) no. of separate device addresses additional information 02 see figure 2 1 1 (main device only) see figure 3 table 4. aden address configuration aden adfix auxiliary address main address 00 a0h * 01 a0h eeprom (table 01, 8ch) 10 n/a * 11 n/a eeprom (table 01, 8ch) table 5. aden and adfix bits main device mon look-up t able control r0 look-up t able auxiliary device 0 dec 0 95 96 127 128 143 199 memory partition with aden bit = 0 en en en en sel en sel 7fh 7fh 80h 80h 60h c7h f0h ffh reserved reserved 8fh 5fh t able select main device enable auxiliary device enable decoder 0 f0h ffh r1 look-up t able en sel 80h c7h table 03 table 02 table 01 figure 2. memory organization, aden = 0 main device mon look-up t able control r0 look-up t able auxiliary device 80h dec 0 95 96 127 128 143 199 255 en en en en sel en sel ffh 7fh 80h 80h c7h f0h ffh reserved reserved 8fh t able select t able 00 main device enable decoder 0 f0h ffh r1 look-up t able en sel 80h c7h table 03 table 02 table 01 memory partition with aden bit = 1 60h 5fh figure 3. memory organization, aden = 1 * 1010a 2 a 1 a 0 r/ w
ds1857 dual temperature-controlled resistors with external temperature input and monitors ____________________________________________________________________ 11 variable resistors the value of each variable resistor is determined by a temperature-addressed look-up table , which can assign a unique value (00h to ffh) to each resistor for every 2? increment over the -40? to +102? range (see table 3). see the temperature conversion section for more information. a resistor disable feature places both outputs in a high- impedance mode. this occurs when the rhiz input is high. an internal pullup of r rhiz is provided, readying this pin for input from the tx disable signal as specified in the sff and sfp msa. the variable resistors can also be used in manual mode. if the ten bit equals 0, then the resistors are in manual mode and the temperature indexing is dis- abled. the user sets the resistors in manual mode by writing to addresses 82h and 83h in table 01 to control resistors 0 and 1, respectively. memory description main and auxiliary memories can be accessed by two separate device addresses. the main device address is determined by address pins or value in table 01 byte 8ch, when adfix = 1 (see table 5). the auxiliary device address is a0h. a user option is provided to respond to one or two device addresses. this feature can be used to save component count in sff applica- tions (main device address can be used) or other applications where both gbic (auxiliary device address can be used) and monitoring functions are implemented and two device addresses are needed. the memory blocks are enabled with the correspond- ing device address. memory space from 80h and up is accessible only through the main device address. this memory is organized as three tables; the desired table can be selected by the contents of memory location 7fh, main device. the auxiliary device address has no access to the tables, but the auxiliary device address can be mapped into the main device? memory space as a fourth table . device addresses are programmable with two control bits in eeprom. aden configures memory access to respond to differ- ent device addresses (see tables 4 and 5). the default device address for eeprom-generated addresses is a2h. if the aden bit is 1, additional 128 bytes of eeprom are accessible through the main device, selected as table 00 (see figure 3). in this configuration, the auxiliary device address is not accessible. apen con- trols the direction of table 00 regardless of the setting of aden. adfix (address fixed) determines whether the main device address is determined by an eeprom byte ( table 01, byte 8ch, when adfix =1). there can be up to 128 devices sharing a common 2-wire bus, with each device having its own unique device address. memory protection memory access from either device address can be either read/write or read only. write protection is accomplished by a combination of control bits in eeprom (apen and mpen in configuration register 89h) and a write-protect enable (wpen) pin. since the wpen pin is often not accessible from outside the mod- ule, this scheme effectively allows the module to be locked by the manufacturer to prevent accidental writes by the end user. separate write protection is provided for the auxiliary and main device address through distinct bits apen and mpen. apen and mpen are bits from configura- tion register 89h, table 01. due to the location, the apen and mpen bits can only be written through the main device address. the control of write privileges through the auxiliary device address is dependent on the value of apen. care should be taken with the set- ting of mpen, once set to a 1, assuming wpen is high, access through the main device is thereafter denied unless wpen is taken to a low level. by this means inadvertent end-user write access can be denied. main device address space 60h to 7fh is sram and is not write protected by apen, mpen, or wpen. for example, the user may reset flags set by the device. bytes designated as ?eserved?may be used as scratchpad but they will not be stored in a power cycle because of their volatility. these bytes are reserved for added functionality in future versions of this device. note that in single device mode (aden bit = 1), apen determines the protection level of table 00, indepen- dent of wpen. the write-protect operation, for both main and auxiliary devices, is summarized in tables 6 and 7. wpen mpen protect main 0x no x0 no 11 yes table 6. main device apen wpen protect auxiliary 0 xno 1 x yes table 7. auxiliary device
ds1857 register map a description of the registers is below. the registers are read only (r) or read/write (r/w). the r/w registers are writable only if write protect has not been asserted (see the memory description section). dual temperature-controlled resistors with external temperature input and monitors 12 ____________________________________________________________________ memory location ( hex) eeprom/sram r/w default setting ( hex) name of location function 00 to 7f eeprom r/w 00 standards data auxiliary device memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 00 to 01 eeprom r/w 00 tmplimhi (msb to lsb) contains upper limit settings for temperature. if the limit is violated, a flag in main device byte 70h is set. 02 to 03 eeprom r/w 00 tmplimlo (msb to lsb) contains lower limit settings for temperature. if the limit is violated, a flag in main device byte 70h is set. 04 to 07 eeprom r 00 reserved 08 to 09 eeprom r/w 00 v cc limhi (msb to lsb) contains upper limit settings for v cc . if the limit is violated, a flag in main device byte 70h is set. 0a to 0b eeprom r/w 00 v cc limlo (msb to lsb) contains lower limit settings for v cc . if the limit is violated, a flag in main device byte 70h is set. 0c to 0f eeprom 00 reserved 10 to 11 eeprom r/w 00 mon1limhi (msb to lsb) contains upper limit settings for mon1. if the limit is violated, a flag in main device byte 70h is set. 12 to 13 eeprom r/w 00 mon1limlo (msb to lsb) contains lower limit settings for mon1. if the limit is violated, a flag in main device byte 70h is set. 14 to 17 eeprom 00 reserved 18 to 19 eeprom r/w 00 mon2limhi (msb to lsb) contains upper limit settings for mon2. if the limit is violated, a flag in main device byte 70h is set. 1a to 1b eeprom r/w 00 mon2limlo (msb to lsb) contains lower limit settings for mon2. if the limit is violated, a flag in main device byte 70h is set. main device note: sram defaults are power-on defaults. eeprom defaults are factory defaults.
ds1857 dual temperature-controlled resistors with external temperature input and monitors ____________________________________________________________________ 13 memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 1c to 5f eeprom 00 reserved 60 to 61 sram r measured tmp (msb to lsb) digitized measured value for temperature. see table 1. 62 to 63 sram r measured v cc (msb to lsb) digitized measured value for v cc . see table 1. 64 to 65 sram r measured mon1 (msb to lsb) digitized measured value for mon1. see table 1. 66 to 67 sram r measured mon2 (msb to lsb) digitized measured value for mon2. see table 1. 68 to 6d sram r reserved 6e sram logic states bit 7 r x hizsta resistor status bit. a high indicates that both resistors are in high-impedance mode. a low indicates that both resistors are operating normally. 6 r/w 0hi zco resistor control bit. setting this bit high causes both resistors to go into a high- impedance state. 5x x 4x x 3x x 2x x 1x x 0 rx rdyb this status bit goes high when v cc has fallen below the poa level. 6f sram conversion updates bit 7 r/w 0 tau this bit goes high after a temperature and address update has occurred for the corresponding measurement in bytes 60h to 61h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. main device (continued)
ds1857 dual temperature-controlled resistors with external temperature input and monitors 14 ____________________________________________________________________ memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 6 r/w 0v cc u this bit goes high after a v cc update has occurred for the corresponding measurement in bytes 62h to 63h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 5 r/w 0 mon1u this bit goes high after a mon1 update has occurred for the corresponding measurement in bytes 64h to 65h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 4 r/w 0 mon2u this bit goes high after a mon2 update has occurred for the corresponding measurement in bytes 66h to 67h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 30 0 20 0 10 x 00 x 70 sram r alarm flags bit 7 tmphi this alarm flag goes high when the upper limit of the temperature setting is violated. 6 tmplo this alarm flag goes high when the lower limit of the temperature setting is violated. 5 v cc hi this alarm flag goes high when the upper limit of the v cc setting is violated. main device (continued)
ds1857 dual temperature-controlled resistors with external temperature input and monitors ____________________________________________________________________ 15 memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 4 v cc lo this alarm flag goes high when the lower limit of the v cc setting is violated. 3 mon1hi this alarm flag goes high when the upper limit of the mon1 setting is violated. 2 mon1lo this alarm flag goes high when the lower limit of the mon1 setting is violated. 1 mon2hi this alarm flag goes high when the upper limit of the mon2 setting is violated. 0 mon2lo this alarm flag goes high when the lower limit of the mon2 setting is violated. 71 sram r alarm flags bit 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 mint a mask of all flags located in table 01 byte 88h determines the value of mint. mint is maskable to 0 if no interrupt is desired by setting table 01 byte 88h to 0. 72 to 7e sram r 00 reserved 7f sram r/w table select bit 7 0 x 60 x 50 x 40 x 30 x 20 x 10 00 table select bits set bits = 00 to select table 00, set bits = 01 to select table 01, set bits = 10 to select table 02, set bits = 11 to select table 03. main device (continued)
ds1857 dual temperature-controlled resistors with external temperature input and monitors 16 ____________________________________________________________________ memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 80 sram r/w mode bit 7 0 x 6? x 5? x 4? x 3? x 2? x 1? ten if ten = 0, the temperature conversions update and the resistors can be controlled manually. the user sets the resistor in manual mode by writing to addresses 82h and 83h in table 01 to control resistors 0 and 1, respectively. 0? aen aen = 0 provides manual control of the temperature index. 81 sram r temp index this byte is the temperature-calculated index used to select the address of resistor settings in the look-up tables. 82 sram r/w 00 resistor 0 resistor 0 position values from 00h to ffh. 83 sram r/w 00 resistor 1 resistor 1 position values from 00h to ffh. 84 to 87 sram 00 reserved 88 eeprom r/w x x bit 7 1 tmp 6? v cc 5 ? mon1 4 ? mon2 3? x 2? x 1? x 0? x 89 eeprom r/w configuration bit 7 0 x 6? x table 01h
ds1857 dual temperature-controlled resistors with external temperature input and monitors ____________________________________________________________________ 17 memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 5 ? aden controls if the device responds to one or two device addresses (see the memory description section and table 5). 4 ? adfix controls the means by which main and auxiliary device addresses are set (see the memory description section and table 5). 3 ? apen c ontr ol s auxi l i ar y w r i te p r otect. s ee the m em or y d escr i p ti on 2? mpen c ontr ol s auxi l i ar y w r i te p r otect. s ee the m em or y d escr i p ti on 1? x 0? x 8a to 8b eeprom ? 0 reserved 8c eeprom r/w a2 device address contains main device address if the bit adfix = 1. if adfix = 0, then address pins determine the address. 8d to 8f eeprom reserved table 01h (continued) memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 80 to c7 eeprom r/w ff resistor 0 temp lut look-up table for resistor 0. f0 to ff eeprom rf f reserved table 02h memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 80 to c7 eeprom r/w ff resistor 1 temp lut look-up table for resistor 1. f0 to ff eeprom rf f reserved table 03h
ds1857 dual temperature-controlled resistors with external temperature input and monitors 18 ____________________________________________________________________ temperature conversion temperature is sensed from an external sensor. the sen- sor? scale is +10mv/? for gain and +500mv for offset at 0?. the ds1857 accommodates a temperature range of -40? to 102? for its look-up tables. the resistor look-up tables are stepped through according to this temperature every 2?. the relationship between the voltage and tem- perature is shown in equation 2. the direct-to-digital temperature sensor measures tem- perature through the use of an on-chip temperature measurement technique with an operating range from -40? to +102?. temperature conversions are initiated upon power-up, and the most recent conversion is stored in memory locations 60h and 61h of the main device, which are updated every t frame . temperature conversions do not occur during an active read or write to memory. the value of each resistor is determined by the tempera- ture-addressed look-up table . the look-up table assigns a unique value to each resistor for every 2? increment with a 1? hysteresis at a temperature transition over the operating temperature range (see figure 4). power-up and low voltage operation during power-up, the device is inactive until vcc exceeds the digital power-on-reset voltage (pod). at this voltage, the digital circuitry, which includes the 2- wire interface, becomes functional. however, eeprom backed registers/settings cannot be internally read (recalled into shadow sram) until v cc exceeds the analog power-on-reset voltage (poa) at which time the remainder of the device becomes fully functional. once vcc exceeds poa, the rdyb bit in byte 6eh of the main device memory is timed to go from a 1 to a 0 and indicates when analog to digital conversions begin. if vcc ever dips below poa, the rdyb bit will read as a 1 again. once a device exceeds poa and the eep- rom is recalled, the values remain active (recalled) until v cc falls below pod. for 2-wire device addresses sourced from eeprom (adfix = 1), the device address defaults to the address determined by the address pins until v cc exceeds poa and the eeprom values are recalled. the auxiliary device (a0h) is always available within this voltage window (between pod and the eeprom recall) regardless of the programmed state of aden. furthermore, as the device powers-up, the vcclo alarm flag (bit 4 of 70h in main device) will default to a 1 until the first v cc analog-to-digital conversion occurs and sets or clears the flag accordingly. 2-wire operation clock and data transitions: the sda pin is normally pulled high with an external resistor or device. data on the sda pin may only change during scl-low time periods. data changes during scl-high periods will indicate a start or stop condition depending on the con- ditions discussed below. see the timing diagrams in figures 5 and 6 for further details. start condition: a high-to-low transition of sda with scl high is a start condition, which must precede any other command. see the timing diagrams in figures 5 and 6 for further details. stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read or write sequence, the stop command places the ds1857 into a low-power mode. see the timing diagrams in figures 5 and 6 for further details. acknowledge: all address and data bytes are trans- mitted through a serial protocol. the ds1857 pulls the sda line low during the ninth clock pulse to acknowl- edge that it has received each word. standby mode: the ds1857 features a low-power mode that is automatically enabled after power-on, after a stop command, and after the completion of all internal operations. device addressing: the ds1857 must receive an 8-bit device address word following a start condition to enable a specific device for a read or write operation. the address word is clocked into this part? msb to lsb. the address byte consists of ah (1010) followed by the value of the address pins (a 1 , a 2 , and a 0) then the r/w bit. this t vv mv = ? 05 10 . (1) m6 m5 m4 m3 m2 m1 2468 10 12 temperature ( c) memory location increasing temperature decreasing temperature figure 4. look-up table temperature hysteresis
ds1857 dual temperature-controlled resistors with external temperature input and monitors ____________________________________________________________________ 19 byte must match the address programmed into table 01 8ch or a0h (for the auxiliary device). if a device address match occurs, this part will output a zero for one clock cycle as an acknowledge and the corresponding block of memory is enabled (see the memory organization sec- tion). if the r/w bit is high, a read operation is initiated. if the r/w is low, a write operation is initiated (see the memory organization section). if the address does not match, this part returns to a low-power mode. write operations after receiving a matching address byte with the r/w bit set low, provided there is no write protect, the device goes into the write mode of operation (see the memory organization section). the master must trans- mit an 8-bit eeprom memory address to the device to define the address where the data is to be written. after the byte has been received, the ds1857 transmits a zero for one clock cycle to acknowledge the address has been received. the master must then transmit an 8-bit data word to be written into this address. the ds1857 again transmits a zero for one clock cycle to acknowledge the receipt of the data. at this point, the master must terminate the write operation with a stop condition. the ds1857 then enters an internally timed write process t w to the eeprom memory. all inputs are disabled during this byte write cycle. page write the ds1857 is capable of an 8-byte page write. a page is any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. for example, addresses 00h through 07h constitute one page. other pages would be addresses 08h through 0fh, 10h through 17h, 18h through 1fh, etc. a page write is initiated the same way as a byte write, but the master does not send a stop condition after the first byte. instead, after the slave acknowledges the data byte has been received, the master can send up to seven more bytes using the same nine-clock sequence. the master must terminate the write cycle with a stop condition or the data clocked into the ds1857 will not be latched into permanent memory. the address counter rolls on a page during a write. the counter does not count through the entire address space as during a read. for example, if the starting address is 06h and 4 bytes are written, the first byte goes into address 06h. the second goes into address 07h. the third goes into address 00h (not 08h). the fourth goes into address 01h. if more than 9 bytes or more are written before a stop condition is sent, the first bytes sent are overwritten. only the last 8 bytes of data are written to the page. acknowledge polling: once the internally timed write has started and the ds1857 inputs are disabled, acknowledge polling can be initiated. the process involves transmitting a start condition followed by the device address. the r/w bit signifies the type of opera- tion that is desired. the read or write sequence will only be allowed to proceed if the internal write cycle has completed and the ds1857 responds with a zero. read operations after receiving a matching address byte with the r/w bit set high, the device goes into the read mode of opera- tion. there are three read operations: current address read, random read, and sequential address read. current address read the ds1857 has an internal address register that main- tains the address used during the last read or write operation, incremented by one. this data is maintained as long as v cc is valid. if the most recent address was the last byte in memory, then the register resets to the first address. once the device address is clocked in and acknowl- edged by the ds1857 with the r/w bit set to high, the current address data word is clocked out. the master does not respond with a zero, but does generate a stop condition afterwards. single read a random read requires a dummy byte write sequence to load in the data byte address. once the device and data address bytes are clocked in by the master, and acknowledged by the ds1857, the master must generate another start condition. the master now initiates a current address read by sending the device address with the r/w bit set high. the ds1857 acknowledges the device address and serially clocks out the data byte. sequential address read sequential reads are initiated by either a current address read or a random address read. after the mas- ter receives the first data byte, the master responds with an acknowledge. as long as the ds1857 receives this acknowledge after a byte is read, the master can clock out additional data words from the ds1857. after reaching address ffh, it resets to address 00h. the sequential read operation is terminated when the master initiates a stop condition. the master does not respond with a zero. for a more detailed description of 2-wire theory of operation, see the following section.
ds1857 dual temperature-controlled resistors with external temperature input and monitors 20 ____________________________________________________________________ 2-wire serial port operation the 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. a device that sends data on the bus is defined as a trans- mitter, and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1857 operates as a slave on the 2-wire bus. connections to the bus are made through the open- drain i/o lines sda and scl. the following i/o termi- nals control the 2-wire serial port: sda, scl. timing diagrams for the 2-wire serial port can be found in figures 5 and 6. timing information for the 2-wire serial port is provided in the ac electrical characteristics table for 2-wire serial communications. the following bus protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line can be changed during the low period of the clock signal. there is one clock pulse per bit of data. figures 5 and 6 detail how data transfer is accomplished on the 2-wire bus. depending upon the state of the r/w bit, two types of data transfer are possible. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications a regular mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1857 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the command/control byte. next follows a number of data bytes. the slave returns an acknowledge bit after each received byte. 2) data transfer from a slave transmitter to a master receiver. the master transmits the first byte (the command/control byte) to the slave. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge can be returned. the master device generates all serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1857 can operate in the following three modes: 1) slave receiver mode: serial data and clock are received through sda and scl, respectively. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recog- nized as the beginning and end of a serial trans- fer. address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit indi- cates that the transfer direction is reversed. serial
ds1857 dual temperature-controlled resistors with external temperature input and monitors ____________________________________________________________________ 21 data is transmitted on sda by the ds1857, while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. 3) slave address: command/control byte is the first byte received following the start condition from the master device. the command/control byte con- sists of a 4-bit control code. for the ds1857, this is set as 1010 binary for read/write operations. the next three bits of the command/control byte are the device select bits or device address. they are used by the master device to select which of eight possible devices on the bus is to be accessed. when reading or writing the ds1857, the device- select bits must match one of two valid device addresses 00h, or the address registered in table 01 location 8ch. the last bit of the command/con- trol byte (r/w) defines the operation to be per- formed. when set to a ??a read operation is selected, and when set to a ??a write operation is selected. the slave address can be set by the eeprom. following the start condition, the ds1857 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1010 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an acknowledge signal on the sda line. chip topology transistor count: 44149 substrate connected to ground. stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 5. 2-wire data transfer protocol
ds1857 dual temperature-controlled resistors with external temperature input and monitors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. dallas is a registered trademark of dallas semiconductor corporation. sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 6. 2-wire ac characteristics

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